公开(公告)号：US20230418617A1

公开(公告)日：2023-12-28

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F12/084 ,  G06T1/60 ,  G06F9/5066 ,  G06F9/544

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20210149680A1

公开(公告)日：2021-05-20

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. APPU

IPC: G06F9/38 ,  G06F12/084 ,  G06F9/54 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20220261075A1

公开(公告)日：2022-08-18

申请号：US17683533

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Ingo WALD ,  Brent E. INSKO ,  Prasoonkumar SURTI ,  Adam T. LAKE ,  Peter L. DOYLE ,  Daniel POHL

IPC: G06F3/01 ,  G02B27/00

Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

公开(公告)号：US20210035348A1

公开(公告)日：2021-02-04

申请号：US17072253

申请日：2020-10-16

Applicant: INTEL CORPORATION

Inventor： Prasoonkumar SURTI ,  Tomas G. AKENINE-MOLLER ,  David J. COWPERTHWAITE ,  Kun TIAN ,  Peter L. DOYLE ,  Brent E. INSKO ,  Adam T. LAKE

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T15/50

Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

公开(公告)号：US20200333879A1

公开(公告)日：2020-10-22

申请号：US16867248

申请日：2020-05-05

Applicant: Intel Corporation

Inventor： Ingo WALD ,  Brent E. INSKO ,  Prasoonkumar SURTI ,  Adam T. LAKE ,  Peter L. DOYLE ,  Daniel POHL

IPC: G06F3/01 ,  G02B27/00

Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

公开(公告)号：US20190102859A1

公开(公告)日：2019-04-04

申请号：US15721063

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： William A. HUX ,  Girish RAVUNNIKUTTY ,  Adam T. LAKE

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/48 ,  G06F9/50

Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including a high priority command streamer to dispatch high priority commands from an application, a normal priority command streamer to receive normal priority commands through a command path, one or more execution units, and a thread dispatcher. The thread dispatcher to dispatch normal priority commands to the one or more executions units, determine the high priority command streamer includes at least one command, cause the one or more execution units to save their states, and dispatch at least one command from the high priority queue to the one or more execution units.