公开(公告)号：US20200227362A1

公开(公告)日：2020-07-16

申请号：US16247312

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Jeffory L. SMALLEY ,  John C. GULICK ,  Phi THANH ,  Mohanraj PRABHUGOUD ,  Chong ZHAO

IPC: H01L23/66 ,  H05K1/18 ,  H01L23/498 ,  H01L23/34 ,  H01B7/04 ,  G02B6/42 ,  H01B3/30 ,  H01B7/08 ,  H01L25/10 ,  H05K1/02

Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

公开(公告)号：US20200229294A1

公开(公告)日：2020-07-16

申请号：US16249499

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Jeffory L. SMALLEY ,  John C. GULICK ,  Phi THANH

IPC: H05K1/02 ,  H01L23/36 ,  H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H05K1/18 ,  H05K1/11

Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a substrate having vias and zones, where the zones have embedded heaters. The heaters may include first traces, second traces, and via filament interconnects. The vias may have a z-height greater than a z-height of the heaters, and each of the zones may have a grid pattern. The RGA interposer may include first and second layers in the substrate, where the first layer includes the first traces, the second layer includes the second traces, and the second layer is over the first layer. The grid pattern may have parallel first traces orthogonal to parallel second traces to form a pattern of squares, where the pattern of squares has the first traces intersect the second traces substantially at right angles.

公开(公告)号：US20200229309A1

公开(公告)日：2020-07-16

申请号：US16249512

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Jeffory L. SMALLEY ,  John C. GULICK ,  Phi THANH

IPC: H05K3/34 ,  H01L23/36 ,  H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.