公开(公告)号：US20200227362A1

公开(公告)日：2020-07-16

申请号：US16247312

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Jeffory L. SMALLEY ,  John C. GULICK ,  Phi THANH ,  Mohanraj PRABHUGOUD ,  Chong ZHAO

IPC: H01L23/66 ,  H05K1/18 ,  H01L23/498 ,  H01L23/34 ,  H01B7/04 ,  G02B6/42 ,  H01B3/30 ,  H01B7/08 ,  H01L25/10 ,  H05K1/02

Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

公开(公告)号：US20210400813A1

公开(公告)日：2021-12-23

申请号：US17354989

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Aaron GORIUS ,  Michael T. CROCKER ,  Matthew J. ADILETTA ,  John C. GULICK ,  Emery E. FREY

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/28 ,  H05K7/02

Abstract: Examples described herein relate to an apparatus that includes a flexible conductor covered in an insulative material and at least one conductor region in contact with the flexible conductor. In some examples, melting of the at least one conductor region is to cause a conductive coupling of the flexible conductor with a second conductor and wherein the flexible conductor is adapted to conductively couple a first circuit board oriented orthogonal to a second circuit board. In some examples, the at least one conductor region comprises at least one solder ball of a grid array. In some examples, the at least one conductor region is re-solderable.

公开(公告)号：US20200229294A1

公开(公告)日：2020-07-16

申请号：US16249499

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Jeffory L. SMALLEY ,  John C. GULICK ,  Phi THANH

IPC: H05K1/02 ,  H01L23/36 ,  H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H05K1/18 ,  H05K1/11

Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a substrate having vias and zones, where the zones have embedded heaters. The heaters may include first traces, second traces, and via filament interconnects. The vias may have a z-height greater than a z-height of the heaters, and each of the zones may have a grid pattern. The RGA interposer may include first and second layers in the substrate, where the first layer includes the first traces, the second layer includes the second traces, and the second layer is over the first layer. The grid pattern may have parallel first traces orthogonal to parallel second traces to form a pattern of squares, where the pattern of squares has the first traces intersect the second traces substantially at right angles.

公开(公告)号：US20210385971A1

公开(公告)日：2021-12-09

申请号：US17337342

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Aaron GORIUS ,  Michael T. CROCKER ,  Jonathan W. THIBADO ,  Matthew J. ADILETTA ,  John C. GULICK ,  Emery E. FREY

IPC: H05K7/20

Abstract: Examples described herein relate to a system. The system can include a container that contains fluid to provide two phase immersion liquid cooling (2PILC) for a system within the container. The container can enclose a first circuit board with a first side of the first circuit board is conductively coupled to at least one device. The container can enclose a motherboard conductively coupled to a second side of the first circuit board with a first side of the motherboard is conductively coupled to the second side of the first circuit board. The motherboard can include at least four edges. Connectors can conductively connect the motherboard with a second circuit board. The second circuit board can include at least four edges and an edge of the motherboard is oriented approximately 90 degrees to an edge of the second circuit board. At least one device can include one or more of: a processor, memory device, accelerator device, or network interface.

公开(公告)号：US20210120663A1

公开(公告)日：2021-04-22

申请号：US17133577

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  John C. GULICK ,  Emery E. FREY

IPC: H05K1/02 ,  H05K7/14

Abstract: An apparatus is described. The apparatus includes a printed circuit board (PCB), a heating element and a layer of material that is physically integrated with a surface of the PCB. The layer of material is to apply an expansive or contractive force to a surface of the PCB in response to being warmed by heat generated by the heating element. The expansive or contractive force is to cause the first surface to expand with a first coefficient of thermal expansion that is closer to a second coefficient of thermal expansion of an opposite surface of the PCB than the surface's coefficient of thermal expansion without the expansive or contractive force.

公开(公告)号：US20200229309A1

公开(公告)日：2020-07-16

申请号：US16249512

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Jonathan W. THIBADO ,  Jeffory L. SMALLEY ,  John C. GULICK ,  Phi THANH

IPC: H05K3/34 ,  H01L23/36 ,  H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.