公开(公告)号：US20220188001A1

公开(公告)日：2022-06-16

申请号：US17689816

申请日：2022-03-08

Applicant: Intel Corporation

Inventor： Ramkumar JAYARAMAN ,  Krishnaprasad H ,  Robert A. BRANCH

IPC: G06F3/06

Abstract: Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and/or applications based on a memory access rate of the VMs/applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs/applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

公开(公告)号：US20230236995A1

公开(公告)日：2023-07-27

申请号：US18127324

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Ramkumar JAYARAMAN ,  Robert BLANKENSHIP ,  Yojan CHITKARA ,  Rahul PAL

IPC: G06F13/16 ,  G06F12/084

CPC classification number: G06F13/1668 ,  G06F12/084 ,  G06F2212/603

Abstract: Techniques to shared system memory across nodes in a system. Circuitry is arranged to provide a mechanism to share a memory region of a memory maintained at a first host CPU at a first node across multiple other host CPUs at multiple other nodes using various links and protocols described in one or more revisions of the Compute Express Link (CXL) specification.