公开(公告)号：US20190042497A1

公开(公告)日：2019-02-07

申请号：US15970639

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  Kenneth FOUST ,  George VERGIS

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G06F13/42 ,  H01R12/72 ,  G11C5/02

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

公开(公告)号：US20220171669A1

公开(公告)日：2022-06-02

申请号：US17671903

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  George VERGIS ,  Myron LOEWEN ,  Matthew A. SCHNOOR

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/42 ,  G06F13/16

Abstract: An apparatus and method to monitor status of a serial data signal on a low speed serial bus is provided. A controller configures a watchdog timer in each target device, sends a heart-beat command to all of the target devices over the low speed serial bus prior to the expiration of the watchdog timer and issues a broadcast read command to any one of the target devices on the low speed serial bus. A response to the broadcast read command confirms that the low speed serial bus is functional. If a response is not received, the low speed serial bus is not functional and the controller initiates a broadcast reset command to initialize all target devices on the low speed serial bus.

公开(公告)号：US20210224206A1

公开(公告)日：2021-07-22

申请号：US17222760

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Rajesh BHASKAR ,  Kenneth FOUST ,  George VERGIS

IPC: G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G06F13/42 ,  G06F1/18 ,  G11C7/10

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.