公开(公告)号：US20230205606A1

公开(公告)日：2023-06-29

申请号：US17922277

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Neelam Chandwani ,  Kshitij Doshi ,  Chetan Hiremath ,  Rajesh Gadiyar ,  Udayan Mukherjee ,  Daniel Towner ,  Valerie Parker ,  Shubha Bommalingaiahnapallya ,  Rany ElSayed

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5044

Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.

公开(公告)号：US20230217253A1

公开(公告)日：2023-07-06

申请号：US17922280

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Rany ElSayed ,  Lokpraveen Mosur ,  Neelam Chandwani ,  Pinkesh Shah ,  Rajesh Gadiyar ,  Shrikant M. Shah ,  Uzair Qureshi

IPC: H04W12/125 ,  G06F9/50

CPC classification number: H04W12/125 ,  G06F9/505

Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.