公开(公告)号：US20230187407A1

公开(公告)日：2023-06-15

申请号：US17548304

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Carleton L. Molnar ,  Adel A. Elsherbini ,  Tanay Karnik ,  Shawna M. Liff ,  Robert J. Munoz ,  Julien Sebot ,  Johanna M. Swan ,  Nevine Nassif ,  Gerald S. Pasdast ,  Krishna Bharath ,  Neelam Chandwani ,  Dmitri E. Nikonov

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/08 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/08147 ,  H01L2924/37001 ,  H01L2924/1427

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

公开(公告)号：US10078522B2

公开(公告)日：2018-09-18

申请号：US13977635

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F1/20 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F15/78 ,  G06F17/30 ,  G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/445 ,  G06F9/4401

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F16/2282 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US20230205606A1

公开(公告)日：2023-06-29

申请号：US17922277

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Neelam Chandwani ,  Kshitij Doshi ,  Chetan Hiremath ,  Rajesh Gadiyar ,  Udayan Mukherjee ,  Daniel Towner ,  Valerie Parker ,  Shubha Bommalingaiahnapallya ,  Rany ElSayed

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5044

Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.

公开(公告)号：US11290923B2

公开(公告)日：2022-03-29

申请号：US16648756

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Mustafa Akdeniz ,  Dave A. Cavalcanti ,  Thorsten Clevorn ,  Brent Elliott ,  Jeffrey R. Foerster ,  Mikhail T. Galeev ,  Benjamin Grewell ,  Nageen Himayat ,  Shadi Iskander ,  Udayan Mukherjee ,  Harry G. Skinner ,  Susruth Sudhakaran ,  Candy Yiu ,  Chetan Hiremath ,  Neelam Chandwani ,  Jesus Martinez

IPC: H04W36/00 ,  H04W4/70 ,  H04W76/11 ,  H04L5/00 ,  H04W64/00 ,  H04W24/10 ,  H04W72/12

Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.

公开(公告)号：US20190065211A1

公开(公告)日：2019-02-28

申请号：US16050240

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F9/4401 ,  G06F11/30 ,  G06F17/30 ,  G06F1/26 ,  G06F1/28 ,  G06F11/36 ,  G06F1/32 ,  G06F9/22 ,  G06F9/445 ,  G06F9/44 ,  G06F11/34 ,  G06F1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US12120595B2

公开(公告)日：2024-10-15

申请号：US17598165

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Chetan Hiremath ,  Rajesh Gadiyar ,  Jason K. Smith ,  Valerie J. Parker ,  Udayan Mukherjee ,  Neelam Chandwani ,  Francesc Guim Bernat ,  Ned M. Smith

IPC: H04W48/02 ,  H04B7/185 ,  H04B7/195 ,  H04W16/28 ,  H04W84/06

CPC classification number: H04W48/02 ,  H04B7/18519 ,  H04B7/18521 ,  H04B7/195 ,  H04W16/28 ,  H04W84/06

Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

公开(公告)号：US11775298B2

公开(公告)日：2023-10-03

申请号：US16933369

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3887

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

公开(公告)号：US10514931B2

公开(公告)日：2019-12-24

申请号：US16050240

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F1/20 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F15/78 ,  G06F16/22 ,  G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/445

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US10007528B2

公开(公告)日：2018-06-26

申请号：US13683748

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Paul Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann ,  Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas ,  Neelam Chandwani ,  Michael A. Rothman ,  Robert Gough ,  Mark Doran

IPC: G06F17/30 ,  G06F9/4401 ,  G06F9/44 ,  G06F9/445 ,  G06F1/28 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/30 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F16/2282 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US12248783B2

公开(公告)日：2025-03-11

申请号：US18369082

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

IPC: G06F1/3203 ,  G06F9/30 ,  G06F9/38

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.