公开(公告)号：US11792123B2

公开(公告)日：2023-10-17

申请号：US17209152

申请日：2021-03-22

Applicant: Intel Corporation

Inventor： Naveed Alam ,  Dhruba Deka ,  Ravindra Singh

IPC: H04B10/00 ,  H04L45/00 ,  H04L12/18 ,  H04L1/00 ,  H04B10/27 ,  H04J14/00

CPC classification number: H04L45/72 ,  H04B10/27 ,  H04L1/004 ,  H04L12/18

Abstract: Examples relate to a transmission apparatus, transmission device, transmission method and computer program for a source device, and to a reception apparatus, reception device, reception method and computer program for a destination device. The transmission apparatus is suitable for generating a header of a transmission frame to be transmitted downstream from a source device to a plurality of destination devices via a point to multipoint communication network. The transmission apparatus comprises processing circuitry configured to generate the header based on a plurality data units to be transmitted to the destination devices. Each data unit is designated to be transmitted to one of the destination devices. The processing circuitry wherein the header is generated such, that the header comprises, for each destination device, information on a presence of data for the destination device in the transmission frame associated with the header.

公开(公告)号：US12028194B2

公开(公告)日：2024-07-02

申请号：US17753089

申请日：2020-09-28

Applicant: Intel Corporation

Inventor： Rainer Strobel ,  Ravindra Singh

IPC: H04L25/06 ,  H03M13/11 ,  H03M13/41 ,  H04L25/03

CPC classification number: H04L25/067 ,  H03M13/1125 ,  H03M13/4146 ,  H04L25/03038 ,  H04L25/03286

Abstract: A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.