公开(公告)号：US10304814B2

公开(公告)日：2019-05-28

申请号：US15640148

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Konika Ganguly ,  Robert J. Royer, Jr. ,  Rebecca Z. Loop ,  Anthony M. Constantine ,  Bilal Khalaf

IPC: G11C14/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/498

Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.