公开(公告)号：US11894334B2

公开(公告)日：2024-02-06

申请号：US16160212

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Yuhong Cai ,  Bilal Khalaf ,  Yi Xu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/48011 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire.

公开(公告)号：US10304814B2

公开(公告)日：2019-05-28

申请号：US15640148

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Konika Ganguly ,  Robert J. Royer, Jr. ,  Rebecca Z. Loop ,  Anthony M. Constantine ,  Bilal Khalaf

IPC: G11C14/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/498

Abstract: An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.

公开(公告)号：US09871007B2

公开(公告)日：2018-01-16

申请号：US14866576

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： John G. Meyers ,  Bilal Khalaf ,  Sireesha Gogineni ,  Brian J. Long

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/58 ,  H01L21/52 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/52 ,  H01L22/32 ,  H01L22/34 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15162 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15333 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

公开(公告)号：US11373974B2

公开(公告)日：2022-06-28

申请号：US16306879

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Bilal Khalaf ,  Mao Guo

IPC: H01L23/00 ,  H01L25/065

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

公开(公告)号：US20220181306A1

公开(公告)日：2022-06-09

申请号：US17681354

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Bilal Khalaf

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.

公开(公告)号：US20210202442A1

公开(公告)日：2021-07-01

申请号：US16087543

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Bilal Khalaf

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.

公开(公告)号：US10475766B2

公开(公告)日：2019-11-12

申请号：US15473544

申请日：2017-03-29

Applicant: INTEL CORPORATION

Inventor： Bilal Khalaf

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: Examples herein include a solid state drive microelectronics package assembly including a substrate and a plurality of microelectronic components coupled to the substrate. The plurality of microelectronic components may be being separated from one another end-to-end by a component gap. The microelectronics package may further include a die package coupled to the substrate, wherein the die package extends across the component gap and is vertically disposed between the plurality of microelectronic components and the substrate. In some examples, the microelectronics components and the die package are each coupled to the substrate by a plurality of connection components (e.g. a solder ball array). The plurality of connection components may be arranged on the microelectronics components to define one or more open areas devoid of any connection components. The die package may be positioned/nested within the one or more open areas to increase overall microelectronic component density of the microelectronics package.

公开(公告)号：US20170025400A1

公开(公告)日：2017-01-26

申请号：US14809132

申请日：2015-07-24

Applicant: Intel Corporation

Inventor： Bilal Khalaf

IPC: H01L25/18 ,  G06F3/06 ,  H01L25/00

CPC classification number: H01L25/18 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  H01L23/538 ,  H01L25/50 ,  H01L2224/16225

Abstract: Techniques and mechanisms for a SIP to control access to a non-volatile memory of another packaged device. In an embodiment, the SIP includes interface a processor, a local memory and a memory controller that provides the processor with access to the local memory. The SIP further includes interface hardware to couple the SIP to the packaged device, wherein the processor of the SIP accesses a non-volatile memory of the packaged device via the memory controller of the SIP. In another embodiment, the interface hardware of the SIP includes a first plurality of contacts to couple to the packaged device, as well as a second plurality of contacts. An interface standard describe an arrangement of interface contacts, wherein, of a first arrangement of the first contacts and the second arrangement of the second contacts, only the second arrangement conforms to the described arrangement of interface contacts.

Abstract translation: 用于SIP控制对另一封装设备的非易失性存储器的访问的技术和机制。 在一个实施例中，SIP包括处理器，本地存储器和为处理器提供对本地存储器的访问的存储器控​​制器的接口。 SIP还包括将SIP耦合到打包设备的接口硬件，其中SIP的处理器经由SIP的存储器控​​制器访问打包设备的非易失性存储器。 在另一个实施例中，SIP的接口硬件包括耦合到封装设备的第一多个触点以及第二多个触点。 接口标准描述了接口触点的布置，其中，第一触点的第一布置和第二触点的第二布置中，只有第二布置符合所描述的界面触点布置。

公开(公告)号：US11848311B2

公开(公告)日：2023-12-19

申请号：US17681354

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Bilal Khalaf

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2225/06568

Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.

公开(公告)号：US11817438B2

公开(公告)日：2023-11-14

申请号：US16247336

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Hyoung Il Kim ,  Bilal Khalaf ,  Juan E. Dominguez ,  John G. Meyers

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265

Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.