公开(公告)号：US20240021500A1

公开(公告)日：2024-01-18

申请号：US18374585

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Robert M. NICKERSON ,  Rees WINTERS ,  Purushotham Kaushik MUTHUR SRINATH

IPC: H01L23/48 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L23/315

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

公开(公告)号：US20230290708A1

公开(公告)日：2023-09-14

申请号：US18318523

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Robert M. NICKERSON ,  Rees WINTERS ,  Purushotham Kaushik MUTHUR SRINATH

IPC: H01L23/48 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L23/315

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

公开(公告)号：US20210066167A1

公开(公告)日：2021-03-04

申请号：US16550773

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Robert M. NICKERSON ,  Rees WINTERS ,  Purushotham Kaushik MUTHUR SRINATH

IPC: H01L23/48 ,  H01L23/31

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

公开(公告)号：US20200035658A1

公开(公告)日：2020-01-30

申请号：US16049696

申请日：2018-07-30

Applicant: Intel Corporation

Inventor： Kumar Abhishek SINGH ,  Zhaozhi LI ,  Thomas J. DEBONIS ,  Robert NICKERSON ,  Rees WINTERS

IPC: H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/544

Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.