公开(公告)号：US20240014097A1

公开(公告)日：2024-01-11

申请号：US18372542

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/373 ,  H01L21/565 ,  H01L23/481 ,  H01L21/02288 ,  H01L21/76816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240006401A1

公开(公告)日：2024-01-04

申请号：US18368424

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. NICKERSON ,  Nicholas R. WATTS

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/105 ,  H05K1/113 ,  H05K3/4038 ,  H01L23/49833 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/50 ,  H01L25/0657 ,  Y10T29/49124 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/32225 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16146 ,  H01L24/32 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L24/48 ,  H01L2224/16238 ,  H01L2224/73265 ,  H01L24/16 ,  H01L2225/1058 ,  H01L2224/13025 ,  H01L2924/15331 ,  H01L2224/32145 ,  H01L2224/0557 ,  H01L2224/0401 ,  H01L2924/00014 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/08238 ,  H01L2224/16227 ,  H01L2224/48245 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15321 ,  H01L2924/381 ,  H01L2224/48106 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/143 ,  H01L2924/1434

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20150171044A1

公开(公告)日：2015-06-18

申请号：US14629350

申请日：2015-02-23

Applicant: INTEL CORPORATION

Inventor： Robert M. NICKERSON ,  Min TAO ,  John S. GUZEK

IPC: H01L23/00 ,  H05K1/18 ,  H01L25/18

CPC classification number: H01L24/19 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/16 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/73259 ,  H01L2224/821 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4682 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.

Abstract translation: 一种包括模具的设备，所述模具包括具有接触点的装置侧的第一侧和相对的第二侧; 以及堆叠载体，其包括设置在所述管芯的第一侧上的至少一层导电材料，以及设置在所述管芯的第二侧上的导电材料和介电材料的多个交替层，其中所述至少一个层 在模具的第一侧上的导电材料的至少一个与模具的第二侧上的（1）至少一个导电材料的交替层中的至少一个耦合，并且（2）至少一个 死。 一种方法，包括邻近模具的一侧形成积聚载体的第一部分，以及与所述模具的另一侧相邻地形成所述堆积载体的第二部分。

公开(公告)号：US20240021500A1

公开(公告)日：2024-01-18

申请号：US18374585

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Robert M. NICKERSON ,  Rees WINTERS ,  Purushotham Kaushik MUTHUR SRINATH

IPC: H01L23/48 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L23/315

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

公开(公告)号：US20230290708A1

公开(公告)日：2023-09-14

申请号：US18318523

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Robert M. NICKERSON ,  Rees WINTERS ,  Purushotham Kaushik MUTHUR SRINATH

IPC: H01L23/48 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L23/315

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

公开(公告)号：US20220157799A1

公开(公告)日：2022-05-19

申请号：US17587664

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. NICKERSON ,  Nicholas R. WATTS

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20210066155A1

公开(公告)日：2021-03-04

申请号：US16557784

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240222350A1

公开(公告)日：2024-07-04

申请号：US18610104

申请日：2024-03-19

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. NICKERSON ,  Nicholas R. WATTS

IPC: H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20240128253A1

公开(公告)日：2024-04-18

申请号：US18399178

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Denis MYASISHCHEV ,  Andrew V. MAZUR ,  Purushotham Kaushik MUTHUR SRINATH ,  Robert M. NICKERSON ,  Shripad GOKHALE

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/315 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

公开(公告)号：US20240128152A1

公开(公告)日：2024-04-18

申请号：US18399205

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/02288 ,  H01L21/565 ,  H01L21/76816 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.