公开(公告)号：US11355199B2

公开(公告)日：2022-06-07

申请号：US16947219

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Wei Cao ,  Richard M. Fastow ,  Xuehong Yu ,  Xin Sun ,  Hyungseok Kim ,  Narayanan Ramanan ,  Amol R. Joshi ,  Krishna Parat

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

公开(公告)号：US20220284968A1

公开(公告)日：2022-09-08

申请号：US17825960

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Wei Cao ,  Richard M. Fastow ,  Xuehong Yu ,  Xin Sun ,  Hyungseok Kim ,  Narayanan Ramanan ,  Amol R. Joshi ,  Krishna Parat

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

公开(公告)号：US20220028459A1

公开(公告)日：2022-01-27

申请号：US16947219

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Wei Cao ,  Richard M. Fastow ,  Xuehong Yu ,  Xin Sun ,  Hyungseok Kim ,  Narayanan Ramanan ,  Amol R. Joshi ,  Krishna Parat

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.