Invention Grant
- Patent Title: Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices
-
Application No.: US16947219Application Date: 2020-07-23
-
Publication No.: US11355199B2Publication Date: 2022-06-07
- Inventor: Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G11C16/26 ; G11C16/04 ; G11C16/32 ; G11C16/08

Abstract:
An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
Public/Granted literature
- US20220028459A1 METHOD AND APPARATUS TO MITIGATE HOT ELECTRON READ DISTURBS IN 3D NAND DEVICES Public/Granted day:2022-01-27
Information query