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公开(公告)号：US20220284968A1
公开(公告)日：2022-09-08
申请号：US17825960
申请日：2022-05-26
Applicant: Intel Corporation
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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公开(公告)号：US20220028459A1
公开(公告)日：2022-01-27
申请号：US16947219
申请日：2020-07-23
Applicant: Intel Corporation
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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Patent Agency Ranking
公开(公告)号：US12087365B2
公开(公告)日：2024-09-10
申请号：US17202137
申请日：2021-03-15
Applicant: Intel Corporation
Inventor： Narayanan Ramanan
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C16/3427
Abstract: Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
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公开(公告)号：US11355199B2
公开(公告)日：2022-06-07
申请号：US16947219
申请日：2020-07-23
Applicant: Intel Corporation
Inventor： Wei Cao , Richard M. Fastow , Xuehong Yu , Xin Sun , Hyungseok Kim , Narayanan Ramanan , Amol R. Joshi , Krishna Parat
Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.
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公开(公告)号：US12266406B2
公开(公告)日：2025-04-01
申请号：US17202133
申请日：2021-03-15
Applicant: Intel Corporation
Inventor： Narayanan Ramanan
Abstract: Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.
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公开(公告)号：US20210257036A1
公开(公告)日：2021-08-19
申请号：US16790074
申请日：2020-02-13
Applicant: Intel Corporation
Inventor： Xiang Yang , Tarek Ahmed Ameen Beshari , Narayanan Ramanan , Arun Thathachary , Shantanu Rajwade , Matin Amani
Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.
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公开(公告)号：US11094386B1
公开(公告)日：2021-08-17
申请号：US16790074
申请日：2020-02-13
Applicant: Intel Corporation
Inventor： Xiang Yang , Tarek Ahmed Ameen Beshari , Narayanan Ramanan , Arun Thathachary , Shantanu Rajwade , Matin Amani
Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.
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