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公开(公告)号：US20240429888A1
公开(公告)日：2024-12-26
申请号：US18212308
申请日：2023-06-21
Applicant: Intel Corporation
Inventor： Ritesh Bhat , Steven Callender , Peter Baumgartner
Abstract: An integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. Other examples are disclosed and claimed.
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公开(公告)号：US20170187405A1
公开(公告)日：2017-06-29
申请号：US14998107
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Shreyas Sen , Ritesh Bhat , Yanjie Wang , Stefano Pellerano , Christopher Hull , Farhana Sheikh
CPC classification number: H04B1/1027 , H04B1/16 , H04L27/14 , H04W52/0209 , H04W52/0229 , H04W52/0238 , H04W52/0245 , H04W88/06 , Y02D70/1262 , Y02D70/142 , Y02D70/144
Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
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公开(公告)号：US09698838B1
公开(公告)日：2017-07-04
申请号：US14998107
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Shreyas Sen , Ritesh Bhat , Yanjie Wang , Stefano Pellerano , Christopher Hull , Farhana Sheikh
CPC classification number: H04B1/1027 , H04B1/16 , H04L27/14 , H04W52/0209 , H04W52/0229 , H04W52/0238 , H04W52/0245 , H04W88/06 , Y02D70/1262 , Y02D70/142 , Y02D70/144
Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
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