公开(公告)号：US09929775B2

公开(公告)日：2018-03-27

申请号：US14668199

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Chintan S. Thakkar ,  Bryan K. Casper ,  James E. Jaussi

IPC: H04B7/00 ,  H04B5/00 ,  H01P3/16 ,  H01Q13/24

CPC classification number: H04B5/0012 ,  H01P3/16 ,  H01Q13/24 ,  H04B5/0031

Abstract: Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.

公开(公告)号：US20170187405A1

公开(公告)日：2017-06-29

申请号：US14998107

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Ritesh Bhat ,  Yanjie Wang ,  Stefano Pellerano ,  Christopher Hull ,  Farhana Sheikh

IPC: H04B1/10 ,  H04W52/02 ,  H04B1/16 ,  H04L27/14

CPC classification number: H04B1/1027 ,  H04B1/16 ,  H04L27/14 ,  H04W52/0209 ,  H04W52/0229 ,  H04W52/0238 ,  H04W52/0245 ,  H04W88/06 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144

Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.

公开(公告)号：US09455529B2

公开(公告)日：2016-09-27

申请号：US14286445

申请日：2014-05-23

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Chintan S. Thakkar ,  James E. Jaussi ,  Bryan K. Casper

IPC: H01R12/00 ,  H01R13/6461 ,  H01R43/20 ,  H01R13/6586 ,  H01R13/6598 ,  H01R13/652 ,  H01R13/627 ,  G06F3/044 ,  H01R13/6464 ,  H01R13/62 ,  H01R13/66

CPC classification number: H01R13/6461 ,  G06F3/044 ,  G06F2203/04108 ,  H01R13/6205 ,  H01R13/627 ,  H01R13/6464 ,  H01R13/652 ,  H01R13/6586 ,  H01R13/6598 ,  H01R13/6625 ,  H01R43/20 ,  Y10T29/435

Abstract: Techniques for forming high-bandwidth proximity connection between capacitively coupled plug and receptacle are described herein. A system for achieving capacitive coupling between contactless pads is described. The techniques include aligning and retaining the plug and receptacle in close proximity to one another. The techniques include cancelling crosstalk in the system based on the symmetry and orientation of differential pairs comprising signal pads. The techniques include enabling a high-bandwidth proximity transmission by filtering the transmission using a silicon buffer component.

Abstract translation: 本文描述了用于在电容耦合插头和插座之间形成高带宽接近连接的技术。 描述了用于实现非接触焊盘之间的电容耦合的系统。 这些技术包括将插头和插座对准并保持彼此靠近。 这些技术包括基于包括信号焊盘的差分对的对称性和取向来消除系统中的串扰。 这些技术包括通过使用硅缓冲器组件对传输进行滤波来实现高带宽接近传输。

公开(公告)号：US09698838B1

公开(公告)日：2017-07-04

申请号：US14998107

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Ritesh Bhat ,  Yanjie Wang ,  Stefano Pellerano ,  Christopher Hull ,  Farhana Sheikh

IPC: H04B1/10 ,  H04L27/14 ,  H04W52/02 ,  H04B1/16 ,  H04W88/06

CPC classification number: H04B1/1027 ,  H04B1/16 ,  H04L27/14 ,  H04W52/0209 ,  H04W52/0229 ,  H04W52/0238 ,  H04W52/0245 ,  H04W88/06 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144

Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.

公开(公告)号：US09584164B1

公开(公告)日：2017-02-28

申请号：US15049616

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Amy L. Whitcombe ,  Erkan Alpman ,  Yanjie Wang ,  Shreyas Sen

IPC: H04B1/00 ,  H04B1/10 ,  H04L27/00

CPC classification number: H04B1/0042 ,  H04B1/10 ,  H04L27/0002

Abstract: A mixer-first receiver operates to generate filtering and analog-to-digital conversion concurrently and adaptively, while removing an LNA before a mixer to enable integration with digital baseband circuits. A plurality of switching capacitor arrays are integrated with a hybrid analog-to-digital filtering component. Switching capacitor arrays of the plurality of switching capacitor arrays can be selectively modified to perform both the filtering operation and the conversion operation together. The same switch capacitors of a switching capacitor array can be utilized in one phase of a clock cycle for the filtering and in another phase of the clock cycle for the conversion.

Abstract translation: 混频器第一接收机用于同时和自适应地产生滤波和模数转换，同时在混频器之前去除LNA以实现与数字基带电路的集成。 多个开关电容器阵列与混合模数转换组件集成。 可以选择性地修改多个开关电容器阵列的开关电容器阵列以一起执行滤波操作和转换操作。 开关电容器阵列的相同开关电容器可以在用于滤波的时钟周期的一个阶段中用于转换的时钟周期的另一个阶段。

公开(公告)号：US20160285513A1

公开(公告)日：2016-09-29

申请号：US14668199

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Chintan S. Thakkar ,  Bryan K. Casper ,  James E. Jaussi

IPC: H04B5/00 ,  H04W76/04 ,  H01P3/16

CPC classification number: H04B5/0012 ,  H01P3/16 ,  H01Q13/24 ,  H04B5/0031

Abstract: Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供用于邻近通信的装置和系统。 该装置可以包括具有中央处理单元（CPU）电路，与CPU电路耦合的输入输出（I / O）电路和与I / O电路耦合的介电电磁波导的集成电路（IC）封装， 以实现CPU电路和另一装置之间的通信。 在另一种情况下，该设备可以包括设置在设备的第一表面上的多个耦合器焊盘; 以及与耦合器焊盘电耦合的处理器。 响应于第一表面与第二表面至少部分接触的布置，耦合器中的一个可以与设置在另一装置的第二表面上的耦合器焊盘之一形成电容耦合，以使处理器之间的接近数据通信 和另一台设备。 可以描述和/或要求保护其他实施例。