公开(公告)号：US20190297015A1

公开(公告)日：2019-09-26

申请号：US16435328

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/773 ,  G06F12/1081 ,  H04L12/861

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20240314072A1

公开(公告)日：2024-09-19

申请号：US18417570

申请日：2024-01-19

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L45/74 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/90

CPC classification number: H04L45/742 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/9068

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20210112003A1

公开(公告)日：2021-04-15

申请号：US17129756

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20200319812A1

公开(公告)日：2020-10-08

申请号：US16909693

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Yadong LI ,  Ziye YANG ,  Changpeng LIU ,  Banghao YING ,  Robert O. SHARP

IPC: G06F3/06

Abstract: Examples described herein relate to accessing an initiator as a Non-Volatile Memory Express (NMVe) device. In some examples, the initiator is configured with an address space, configured in kernel or user space, for access by a virtualized execution environment. In some examples, the initiator to copy one or more storage access commands from the virtualized execution environment into a queue for access by a remote direct memory access (RDMA) compatible network interface. In some examples, the network interface to provide Non-Volatile Memory Express over Fabrics (NVMe-oF) compatible commands based on the one or more storage access commands to a target storage device. In some examples, the initiator is created as a mediated device in kernel space or user space of a host system. In some examples, configuration of a physical storage pool address of the target storage device for access by the virtualized execution environment occurs by receipt of the physical storage pool address in a configuration command. In some examples, configuration of the target storage device for access by the virtualized execution environment occurs by receipt of a storage pool internal NVMe Qualified Name in the configuration command.

公开(公告)号：US20200042350A1

公开(公告)日：2020-02-06

申请号：US16594819

申请日：2019-10-07

Applicant: Intel Corporation

Inventor： Manasi DEVAL ,  Neerav PARIKH ,  Robert O. SHARP ,  Gregory J. BOWERS ,  Ryan E. HALL ,  Chinh T. CAO

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50

Abstract: Tenant support is provided in a multi-tenant configuration in a data center by a Physical Function driver communicating a virtual User Priority to a virtual traffic class mapper to a Virtual Function driver. The Physical Function driver configures the Network Interface Controller to map virtual User Priorities to Physical User Priorities and to enforce the Virtual Function's limited access to Traffic Classes. Data Center Bridging features assigned to the physical network interface controller are hidden by virtualizing user priorities and traffic classes. A virtual Data Center Bridging configuration is enabled for a Virtual Function, to provide access to the user priorities and traffic classes that are not visible to the Virtual Function that the Virtual Function may need.