公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.