公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.

公开(公告)号：US12266527B1

公开(公告)日：2025-04-01

申请号：US17559406

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Eungnak Han ,  Xuanxuan Chen ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein ,  David Nathan Shykind ,  Thomas Christopher Hoff

IPC: H01L21/027

Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

公开(公告)号：US12293913B1

公开(公告)日：2025-05-06

申请号：US17559363

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Gurpreet Singh ,  Richard E. Schenker ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Gauri Nabar ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein

IPC: H01L23/532 ,  H01L21/027

Abstract: Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.