公开(公告)号：US20250113603A1

公开(公告)日：2025-04-03

申请号：US18374608

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Munzarin QAYYUM ,  Rohit GALATAGE ,  Marko RADOSAVLJEVIC ,  Cheng-Ying HUANG ,  Evan CLINTON ,  David BENNETT ,  Jami WIEDEMER

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating depopulated channel structures using split source or drain approaches, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires, the first vertical arrangement of nanowires having one or more dielectric nanowires coupled to a dielectric source or drain structure. A first gate stack is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires having one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure laterally spaced apart from the dielectric source or drain structure. A second gate stack is over the second vertical arrangement of nanowires.