公开(公告)号：US20230206383A1

公开(公告)日：2023-06-29

申请号：US17561666

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Vidhya KRISHNAN ,  Aditya NAVALE ,  Abhishek R. APPU ,  Altug KOKER ,  Ronald W. SILVAS

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/084

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/084 ,  G06F2212/401

Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

公开(公告)号：US20230030741A1

公开(公告)日：2023-02-02

申请号：US17390661

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Nilay MISTRY ,  Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Ronald W. SILVAS

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/30

Abstract: Compressed verbatim copy can enable more efficient copying of compressed data. In one example, a compressed verbatim copy method involves receiving a command to copy compressed data from a source address of the memory device to a destination address. In response to the receipt of the command, the method involves copying the compressed data in a compressed format from the source address to the destination address without first decompressing the data. A second source address and a second destination address of metadata for the compressed data is determined, and the metadata is copied from the second source address to the second destination address.

公开(公告)号：US20160328823A1

公开(公告)日：2016-11-10

申请号：US15154357

申请日：2016-05-13

Applicant: INTEL CORPORATION

Inventor： Jayanth N. RAO ,  Ronald W. SILVAS ,  Ankur N. SHAH

IPC: G06T1/60 ,  G06F12/02 ,  G06F12/084 ,  G06T1/20 ,  G06F12/1009

CPC classification number: G06T1/60 ,  G06F12/0223 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/126 ,  G06F2212/302 ,  G06F2212/62 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/20 ,  G06T11/60 ,  Y02D10/13

Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.

Abstract translation: 本文公开了一种用于计算设备的中央处理单元（CPU）和图形处理单元（GPU）之间的共享虚拟存储器的方法和系统。 该方法包括在系统存储器内分配表面。 可以创建CPU虚拟地址空间，并且可以将表面映射到CPU页表中的CPU虚拟地址空间。 该方法还包括创建等效于CPU虚拟地址空间的GPU虚拟地址空间，将表面映射到GPU页表中的GPU虚拟地址空间，并固定表面。

公开(公告)号：US20220197651A1

公开(公告)日：2022-06-23

申请号：US17131633

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Gaurav KUMAR ,  Changliang L. WANG ,  Haichun DAI ,  Hongbin YE ,  Ronald W. SILVAS

IPC: G06F9/30 ,  G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a system that after decoding of video by the first device, provides a memory address of decoded video in the memory device to a second driver for a second device and perform a second device driver that causes the second device to access the decoded video directly from a translation of the memory address of the memory device, wherein the second device is to access the decoded video with memory properties of the decoded video and decompression information of the decoded video. In some examples, the first device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU), a discrete graphics processing unit, or a video decoder accelerator. In some examples, the second device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU) or a discrete graphics processing unit. In some examples, the memory properties of the decoded video comprise swizzle information. In some examples, decompression information of the decoded video comprise a decompression scheme or decompression key.