公开(公告)号：US20220398147A1

公开(公告)日：2022-12-15

申请号：US17849356

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Balaji VEMBU ,  Bryan WHITE ,  Ankur SHAH ,  Murali RAMADOSS ,  David PUFFER ,  Altug KOKER ,  Aditya NAVALE ,  Mahesh NATU

IPC: G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

公开(公告)号：US20150348222A1

公开(公告)日：2015-12-03

申请号：US14292064

申请日：2014-05-30

Applicant: Intel Corporation

Inventor： Prasoonkumar SURTI ,  Aditya NAVALE

IPC: G06T1/20 ,  G06T15/80

CPC classification number: G06T1/20

Abstract: An apparatus and method for identifying sub-groups of execution resources for parallel pixel processing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first set of one or more modulus operations using even bits from the X and Y coordinates to generate a first intermediate result; performing a second set of one or more modulus operations using odd bits from the X and Y coordinates to generate a second intermediate result; comparing the first intermediate result and the second intermediate result to generate a final result; and using the final result to select a first set of processing resources from a set of N processing resources for processing the pixel block.

Abstract translation: 一种用于识别用于并行像素处理的执行资源的子组的装置和方法。 例如，方法的一个实施例包括：确定要处理的像素块的X和Y坐标; 使用来自X和Y坐标的偶数位执行第一组一个或多个模运算，以产生第一中间结果; 使用来自X和Y坐标的奇数位执行第二组一个或多个模运算，以产生第二中间结果; 比较第一中间结果和第二中间结果以产生最终结果; 以及使用最终结果从用于处理像素块的一组N个处理资源中选择第一组处理资源。

公开(公告)号：US20240045725A1

公开(公告)日：2024-02-08

申请号：US17881540

申请日：2022-08-04

Applicant: Intel Corporation

Inventor： Prashant CHAUDHARI ,  Jain PHILIP ,  James VALERIO ,  Murali RAMADOSS ,  Ankur SHAH ,  Jeffery S. BOLES ,  Aditya NAVALE

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/5044 ,  G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45583

Abstract: Apparatus and method for concurrent performance monitoring. For example, one embodiment of an apparatus comprises: compute hardware logic to concurrently process a number of workloads, the compute hardware logic to be subdivided into a plurality of compute hardware contexts based on the number of workloads; and programmable performance monitoring circuitry to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier associated with each of the compute hardware contexts.

公开(公告)号：US20230206383A1

公开(公告)日：2023-06-29

申请号：US17561666

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Vidhya KRISHNAN ,  Aditya NAVALE ,  Abhishek R. APPU ,  Altug KOKER ,  Ronald W. SILVAS

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/084

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/084 ,  G06F2212/401

Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

公开(公告)号：US20210271539A1

公开(公告)日：2021-09-02

申请号：US17171790

申请日：2021-02-09

Applicant: Intel Corporation

Inventor： Balaji VEMBU ,  Bryan WHITE ,  Ankur SHAH ,  Murali RAMADOSS ,  David PUFFER ,  Altug KOKER ,  Aditya NAVALE ,  Mahesh NATU

IPC: G06F11/07

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.