公开(公告)号：US12166124B2

公开(公告)日：2024-12-10

申请号：US16913294

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Ryan Hickey ,  Glenn A. Glass ,  Anand S. Murthy ,  Rushabh Shah ,  Ju-Hyung Nam

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/167

Abstract: Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.

公开(公告)号：US20230197724A1

公开(公告)日：2023-06-22

申请号：US17557517

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy ,  Glenn Glass ,  Rushabh Shah ,  Susmita Ghose

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66742

Abstract: An integrated circuit structure includes a first non-planar semiconductor device and a second non-planar semiconductor device. The first non-planar semiconductor device includes a first body, a first gate structure at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body, a second gate structure at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height of the first body is at least 5% different from a second height of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：US20230178658A1

公开(公告)日：2023-06-08

申请号：US17540560

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Glenn Glass ,  Anand Murthy ,  Rushabh Shah

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L21/0259 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: A semiconductor structure includes a body including semiconductor material, and a gate structure at least in part wrapped around the body. The semiconductor structure further includes a source region and a drain region, the body laterally extending between the source and drain regions. The body has a middle region between first and second tip regions. In an example, the source region at least in part wraps around the first tip region of the body, and/or the drain region at least in part wraps around the second tip region of the body. In another example, the body includes a core structure and a peripheral structure (e.g., cladding or layer that wraps around the core structure in the middle region of the body) that is compositionally different from the core structure. The body can be, for instance, a nanoribbon, nanosheet, or nanowire or a gate-all-around device or a forksheet device.