公开(公告)号：US20170147054A1

公开(公告)日：2017-05-25

申请号：US15426876

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  JAY D. SCHWARTZ ,  SHARAD C. TRIPATHI

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.