公开(公告)号：US20250113600A1

公开(公告)日：2025-04-03

申请号：US18477947

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Yulia Gotlib ,  Matthew J. Prince ,  Sachin S. Vaidya ,  Ying Zhou ,  Xiaoye Qin ,  Ryan Pearce ,  Andrew Arnold ,  Chiao-Ti Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.