公开(公告)号：US20250113600A1

公开(公告)日：2025-04-03

申请号：US18477947

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Yulia Gotlib ,  Matthew J. Prince ,  Sachin S. Vaidya ,  Ying Zhou ,  Xiaoye Qin ,  Ryan Pearce ,  Andrew Arnold ,  Chiao-Ti Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.

公开(公告)号：US20230369509A1

公开(公告)日：2023-11-16

申请号：US17742638

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Jisoo Kim ,  Xiaoye Qin ,  Timothy Jen ,  Harish Ganapathy ,  Van H. Le ,  Huiying Liu ,  Prem Chanani ,  Cheng Tan ,  Shailesh Kumar Madisetti ,  Abhishek Anil Sharma ,  Brian Wadsworth ,  Vishak Venkatraman ,  Andre Baran

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/7869 ,  H01L23/5283 ,  H01L27/10814

Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.

公开(公告)号：US20240332071A1

公开(公告)日：2024-10-03

申请号：US18129704

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Alireza Narimannezhad ,  Vladislav Kamysbayev ,  Xiaoye Qin ,  Sunzida Ferdous ,  Reken Patel

IPC: H01L21/768 ,  C23C16/40 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76834 ,  C23C16/401 ,  C23C16/45538 ,  C23C16/50 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/0228 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53257

Abstract: A low-leakage oxide dielectric material with high elastic modulus is deposited directly upon an oxidizable feature with a polycyclic PE-ALD process that limits the formation of an oxide on the feature. A precursor of one or more constituents, such as silicon, may be deposited upon a workpiece during a deposition phase, and the absorbed precursor(s) may be oxidized during a first oxidation phase under more conservative conditions until a first film thickness is achieved. Subsequently, absorbed precursor(s) may be oxidized during a second oxidation phase under more aggressive conditions to arrive at a total film thickness. Transistor contact metal, which may provide local interconnection between source or drain terminals of multiple transistors, may maintain high electrical conductivity after being electrically insulated with such a low-leakage film.

公开(公告)号：US20230197840A1

公开(公告)日：2023-06-22

申请号：US17557827

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Xiaoye Qin ,  Johann C. Rode ,  Atsunori Tanaka ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7785 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.