公开(公告)号：US20230273733A1

公开(公告)日：2023-08-31

申请号：US18312289

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Sagar Varma Sayyaparaju ,  Pramod Udupa ,  Dinesh Kushwaha

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673

Abstract: Systems and methods include technology that receives, with a plurality of cores implemented in one or more of configurable logic or fixed-functionality logic, data associated with a workload, and executing, with the plurality of cores, the workload to process the data and generate partial data. The technology stores the partial data into a memory storage that is accessible by the plurality of cores as the workload is being executed.

公开(公告)号：US20240201949A1

公开(公告)日：2024-06-20

申请号：US18590495

申请日：2024-02-28

Applicant: Intel Corporation

Inventor： Sagar Varma Sayyaparaju ,  Om Ji Omer ,  Sreenivas Subramoney

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50

Abstract: Systems, apparatuses and methods may provide for technology that includes a compute-in-memory (CiM) enabled memory array to conduct digital bit-serial multiply and accumulate (MAC) operations on multi-bit input data and weight data stored in the CiM enabled memory array, an adder tree coupled to the CiM enabled memory array, an accumulator coupled to the adder tree, and an input bit selection stage coupled to the CiM enabled memory array, wherein the input bit selection stage restricts serial bit selection on the multi-bit input data to non-zero values during the digital MAC operations.