公开(公告)号：US20220114270A1

公开(公告)日：2022-04-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren WANG ,  Sameh GOBRIEL ,  Somnath PAUL ,  Yipeng WANG ,  Priya AUTEE ,  Abhirupa LAYEK ,  Shaman NARAYANA ,  Edwin VERPLANKE ,  Mrittika GANGULI ,  Jr-Shian TSAI ,  Anton SOROKIN ,  Suvadeep BANERJEE ,  Abhijit DAVARE ,  Desmond KIRKPATRICK

IPC: G06F21/62

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US20210089216A1

公开(公告)日：2021-03-25

申请号：US17099653

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Yipeng WANG ,  Ren WANG ,  Sameh GOBRIEL ,  Tsung-Yuan C. TAI

IPC: G06F3/06 ,  G06F12/128 ,  H04L12/747 ,  G06F12/0875

Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.

公开(公告)号：US20230082780A1

公开(公告)日：2023-03-16

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin SUN ,  Yipeng WANG ,  Rahul R. SHAH ,  Ren WANG ,  Sameh GOBRIEL ,  Hongjun NI ,  Mrittika GANGULI ,  Edwin VERPLANKE

IPC: G06F9/50

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

公开(公告)号：US20190004709A1

公开(公告)日：2019-01-03

申请号：US15639821

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yipeng WANG ,  Ren WANG ,  Sameh GOBRIEL ,  Tsung-Yuan Charlie TAI

IPC: G06F3/06 ,  G06F12/128

Abstract: Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.