公开(公告)号：US20210073129A1

公开(公告)日：2021-03-11

申请号：US17086243

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Rahul R. SHAH ,  Omkar MASLEKAR ,  Priya AUTEE ,  Edwin VERPLANKE ,  Andrew J. HERDRICH ,  Jeffrey D. CHAMBERLAIN

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F9/30

Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

公开(公告)号：US20230082780A1

公开(公告)日：2023-03-16

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin SUN ,  Yipeng WANG ,  Rahul R. SHAH ,  Ren WANG ,  Sameh GOBRIEL ,  Hongjun NI ,  Mrittika GANGULI ,  Edwin VERPLANKE

IPC: G06F9/50

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.