公开(公告)号：US20240103077A1

公开(公告)日：2024-03-28

申请号：US17954658

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Sankaran MENON ,  Rolf KUEHNIS

IPC: G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/318533 ,  G01R31/31907 ,  G01R31/31924

Abstract: Time to read the data registers in a remote Test Access Port (TAP) in a subsystem in a System-on-Chip (SoC) is reduced by reading multiple data registers in remote Test Access Ports in parallel. A Test Access Port Bridge provides access to multiple same width data registers in parallel. The same width data registers can be for the same function or different functions. The subsystems with a remote Test Access Port in the SoC can include Peripheral Component Interconnect Express (PCIe), Voltage Droop Monitors (VDMs), In-Die Variation (IDV) Monitor fub-lets, Temperature Sensors, Performance Monitors and telemetry subsystems.