公开(公告)号：US20180285310A1

公开(公告)日：2018-10-04

申请号：US15476506

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Suketu BHATT ,  Satheesh CHELLAPPAN

IPC: G06F13/42 ,  G06F11/22

CPC classification number: G06F13/4291

Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

公开(公告)号：US20240281196A1

公开(公告)日：2024-08-22

申请号：US18571586

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Satheesh CHELLAPPAN ,  Tomasz PIELASZKIEWICZ

IPC: G06F3/16

CPC classification number: G06F3/162

Abstract: A device system-on-a-chip (SoC) includes a streaming audio interface, a local memory, and a device controller coupled to the memory. The device controller is to decode an audio frame to generate a decoded audio frame. The audio frame is received via the streaming audio interface. The decoded audio frame is processed according to a streaming audio protocol to obtain corresponding control data and periodic streaming audio data. The control data is parsed to obtain a memory address pointer. Memory access to the local memory is performed based on the memory address pointer.