公开(公告)号：US20180285310A1

公开(公告)日：2018-10-04

申请号：US15476506

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Suketu BHATT ,  Satheesh CHELLAPPAN

IPC: G06F13/42 ,  G06F11/22

CPC classification number: G06F13/4291

Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.