公开(公告)号：US20180145016A1

公开(公告)日：2018-05-24

申请号：US15355961

申请日：2016-11-18

申请人： Intel Corporation

发明人： Min Suet Lim ,  Mooi Ling Chang ,  Eng Huat Goh ,  Say Thong Tony Tan ,  Tin Poay Chuah

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L21/48

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5386

摘要： Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

公开(公告)号：US10297541B2

公开(公告)日：2019-05-21

申请号：US15355961

申请日：2016-11-18

申请人： Intel Corporation

发明人： Min Suet Lim ,  Mooi Ling Chang ,  Eng Huat Goh ,  Say Thong Tony Tan ,  Tin Poay Chuah

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538

摘要： Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

公开(公告)号：US11096284B2

公开(公告)日：2021-08-17

申请号：US16451542

申请日：2019-06-25

申请人： Intel Corporation

发明人： Wee Hoe ,  Chan Kim Lee ,  Chee Chun Yee ,  Mooi Ling Chang ,  Siang Yeong Tan ,  Say Thong Tony Tan

IPC分类号： G06F1/16 ,  H05K1/18 ,  H01L25/16 ,  H01Q1/22 ,  H01L23/538

摘要： A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.