公开(公告)号：US12256487B2

公开(公告)日：2025-03-18

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Chin Lee Kuan ,  Tin Poay Chuah

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US12061502B2

公开(公告)日：2024-08-13

申请号：US17368851

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Tin Poay Chuah ,  Howe Yin Loo ,  Chin Kung Goh ,  Yew San Lim ,  Cora Shih Wei Nien

IPC: G06F1/20 ,  G06F1/16

CPC classification number: G06F1/203 ,  G06F1/1616

Abstract: According to the present disclosure, a laptop may be provided with a compartment including a moveable segment, an expandable heat exchanger with a movable section, and an expandable fan unit. The release of the movable segment of the compartment from a lower portion of the compartment produces an opening in the compartment and the movable section of the expandable heat exchanger is extended downward, and the expandable fan unit is lowered when the movable segment of the compartment is released.

公开(公告)号：US20230395480A1

公开(公告)日：2023-12-07

申请号：US17834674

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Jeff Ku ,  Min Suet Lim ,  Yew San Lim ,  Twan Sing Loo

IPC: H01L23/498 ,  H05K3/34 ,  H01L21/48 ,  H05K1/11

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K1/115 ,  H05K2201/10734 ,  H05K2201/0154 ,  H05K2201/10303 ,  H01L21/4853

Abstract: A substrate to printed circuit board (PCB) interconnect with liquid metal and surface pins. A thin dielectric sheet with drilled openings is adjacent to the bottom of a system on chip or CPU package substrate. Holes in the dielectric sheet have a liquid metal (LM) therein, the holes correspond to landing metal pads on the package substrate. The PCB includes surface pins in an arrangement to match the LM filled holes. A pick and place assembly of the package substrate to the PCB can be done without needing a reflow step. A magnet ring can be positioned on the polyimide sheet and configured to pair with a metal plate on the PCB. Guideposts around the periphery of the package substrate may be used to assist in alignment during assembly.

公开(公告)号：US11521943B2

公开(公告)日：2022-12-06

申请号：US17229316

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Chin Lee Kuan

IPC: H05K1/18 ,  H01L23/64 ,  H01L23/498 ,  H05K1/02 ,  H01L23/50 ,  H01L23/13

Abstract: A capacitor loop substrate assembly includes a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects are formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US11481001B2

公开(公告)日：2022-10-25

申请号：US17088620

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Chee Chun Yee ,  Tin Poay Chuah ,  Yew San Lim ,  Min Suet Lim ,  Jeff Ku

IPC: G06F1/16

Abstract: According to the various examples, a dual display system having a first panel having a first display area, a second panel having a second display area, and a connector assembly, attached to the first and second panels, that is configured to enable the first and second panels to rotate around three-directional axes. The connector assembly includes an elongated member and a hinge assembly, which are configured for attachment to the first and second display panels. The present dual display system may have several functional modalities, including use as a desktop computer, a laptop computer, a tablet, and a panoramic display.

公开(公告)号：US20220110214A1

公开(公告)日：2022-04-07

申请号：US17550746

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Martin M. Chang ,  Tin Poay Chuah ,  Eng Huat Goh ,  Chu Aun Lim ,  Min Suet Lim

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/30

Abstract: An apparatus comprising a package comprising a first side to interface with at least one chip; and a second side to interface with a circuit board, the second side opposite to the first side, wherein the second side comprises a non-stepped portion comprising a first plurality of conductive contacts; and a stepped portion that protrudes from the non-stepped portion, the stepped portion comprising a second plurality of conductive contacts.

公开(公告)号：US11172581B2

公开(公告)日：2021-11-09

申请号：US16003970

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Tin Poay Chuah ,  Han Kung Chua

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18 ,  H05K3/30

Abstract: Disclosed herein is a multi-planar circuit board, as well as related structures and methods. In an embodiment, a circuit board may include a first surface, a first section having the first surface in a first plane, a second section having the first surface in a second plane, and a third section connecting the first and second sections, where the third section defines a gradient between the first and second planes, and where all sections are sections within a contiguous board. In another embodiment, circuit board may further include a first component having a first thickness coupled on the first face of the first section, and a second component having a second thickness, greater than the first component, coupled on the first face of the second section, where the second section is in a lower plane, and where the overall thickness is the circuit board thickness plus the second thickness.

公开(公告)号：US20210212205A1

公开(公告)日：2021-07-08

申请号：US17212016

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Khai Ern See ,  Jia Lin Liew ,  Tin Poay Chuah ,  Chee How Lim ,  Yi How Ooi

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/00

Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

公开(公告)号：US10856454B2

公开(公告)日：2020-12-01

申请号：US16535766

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC: H05K9/00 ,  H05K3/46 ,  H05K1/11

Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US20190261504A1

公开(公告)日：2019-08-22

申请号：US16399825

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Yew San Lim ,  Boon Ping Koh ,  Phaik Kiau Tan

IPC: H05K1/02 ,  H05K1/14 ,  H05K3/36

Abstract: A folded circuit board includes a first circuit board and a second circuit board. The first circuit board and second circuit board are coupled together through a flexible interconnect. One or more folding guides are coupled to one of the first circuit board or second circuit board. The one or more folding guides extend beyond a first edge of the one of the first circuit board or second circuit board. The one or more folding guides include a curved sidewall configured to guide the flexible interconnect when the first circuit board is folded over the second circuit board. In one embodiment, the one or more folding guides are grounded to reduce EMI emissions.