公开(公告)号：US20230418934A1

公开(公告)日：2023-12-28

申请号：US17849351

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Scott D. Constable ,  Joao Batista Correa Gomes Moreira ,  Alyssa A. Milburn ,  Ke Sun ,  Michael LeMay ,  David M. Durham ,  Joseph Nuzman ,  Jason W. Brandt ,  Anders Fogh

IPC: G06F21/54 ,  G06F21/51

CPC classification number: G06F21/54 ,  G06F21/51 ,  G06F2221/033

Abstract: In one embodiment, an indirect branch is detected in computer program code. The indirect branch calls one of a plurality of functions using a first register. In response, the computer program code is augmented to store an identifier of the indirect branch call in a second register, and the code for each of the plurality of functions is augmented to: determine whether an identifier for the function matches the identifier stored in the second register and render the first register unusable if the identifier for the function does not match the identifier stored in the second register.

公开(公告)号：US20230315465A1

公开(公告)日：2023-10-05

申请号：US17712073

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Scott D. Constable

IPC: G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3802 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems, methods, and apparatuses for implementing capability-based indirect prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability; a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access; a cache; and a prefetch circuit to: prefetch an additional element of the first object from the memory based on the first capability, determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and prefetch the second element from the memory to the cache based on the additional element being the second capability.

公开(公告)号：US20250103512A1

公开(公告)日：2025-03-27

申请号：US18474981

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Thomas Unterluggauer ,  Fangfei Liu ,  Scott D. Constable ,  Carlos V. Rozas ,  Gilles Pokam ,  Boris Dolgunov

IPC: G06F12/14 ,  G06F12/0808

Abstract: Techniques for cache scrubbing for cache-set randomization to resist contention-based cache attacks are described. In certain examples, a system includes a memory; an execution circuit to cause a memory access request for the memory; a cache to store a plurality of sets that each include a plurality of cache lines from the memory; a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request; and a cache scrubber circuit to determine that a number of invalid cache lines in a set of the plurality of sets of the cache is less than a threshold number of invalid cache lines, and in response, invalidate a valid cache line in the set of the plurality of sets of the cache.

公开(公告)号：US20240329995A1

公开(公告)日：2024-10-03

申请号：US18194010

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Scott D. Constable

IPC: G06F9/30 ,  G06F11/10 ,  G06F12/14

CPC classification number: G06F9/3016 ,  G06F11/1004 ,  G06F12/1425 ,  G06F2212/1052

Abstract: Circuitry and methods for implementing one or more predicated capability instructions are described. In certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field for an address to be accessed by the memory access request and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising a field to indicate the capability, and an opcode to indicate: an operation to be performed for the address, that an execution circuit is to perform a first check that a condition code, that indicates a status from a previous execution of the execution circuit, is a certain value, that the capability management circuit is to perform a second check that the capability authorizes access to the address, and in response to the first check and the second check both passing, cause the execution circuit to perform the operation for the address; and the execution circuit to execute the decoded single instruction according to the opcode.

公开(公告)号：US20230315640A1

公开(公告)日：2023-10-05

申请号：US17712072

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Scott D. Constable

IPC: G06F12/0862 ,  G06F12/0875

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F2212/602 ,  G06F2212/452

Abstract: Systems, methods, and apparatuses for implementing capability-directed array prefetching are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory; a capability management circuit to check a capability for the memory access request, the capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of an object to which the capability authorizes access; a cache; and a prefetch circuit to prefetch an additional element of the object from the memory to the cache based on the capability checked by the capability management circuit.

公开(公告)号：US20240330000A1

公开(公告)日：2024-10-03

申请号：US18194086

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Scott D. Constable ,  Michael LeMay

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30145

Abstract: Techniques for implementing forward-edge control-flow integrity (FECFI) using capability instructions in a hardware processor are described. In certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising: a first capability to indicate a first call table comprising a respective entry for each of a plurality of functions of a first type, a field to indicate a first offset of a first entry for a first function requested for execution, and an opcode to indicate the capability management circuit is to perform a first check that the first offset is within a lower bound and an upper bound of the first capability and a second check that the first offset is a permitted offset for the entries in the first call table, and in response to the first check and the second check both passing, cause an execution circuit to execute the first function; and the execution circuit to execute the decoded single instruction according to the opcode.

公开(公告)号：US20230315452A1

公开(公告)日：2023-10-05

申请号：US17712075

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Scott D. Constable

IPC: G06F9/30 ,  G06F12/14 ,  G06F12/0862

CPC classification number: G06F9/30047 ,  G06F9/30145 ,  G06F12/1458 ,  G06F12/0862

Abstract: Systems, methods, and apparatuses for implementing capability informed prefetches are described. In certain examples, a hardware processor comprises an execution circuit to execute an instruction that generates a memory access request for an element in memory via a first capability; a capability management circuit to check the first capability for the memory access request, the first capability comprising an address field of the element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a first object to which the first capability authorizes access; a cache; and a prefetch circuit to: prefetch an additional element from the memory to the cache, determine if the additional element is a second capability comprising an address field of a second element in the memory, a validity field, and a bounds field that is to indicate a lower bound and an upper bound of a second object to which the second capability authorizes access, and prefetch the second element from the memory to the cache based on the additional element being the second capability.