公开(公告)号：US20150007196A1

公开(公告)日：2015-01-01

申请号：US13931657

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： BRET L. TOLL ,  Jason W. Brandt ,  Eliezer Weissmann ,  Inder M. Sodhi ,  David A. Koufaty ,  Scott D. Hanh

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5044 ,  G06F9/5088 ,  Y02D10/22 ,  Y02D10/32

Abstract: A processor of an aspect includes a first heterogeneous physical compute element having a first set of supported instructions and architectural features, and a second heterogeneous physical compute element having a second set of supported instructions and architectural features. The second set of supported instructions and architectural features is different than the first set of supported instructions and architectural features. The processor also includes a workload and architectural state migration module coupled with the first and second heterogeneous physical compute elements. The workload and state migration module is operable to migrate a workload and associated architectural state from the first heterogeneous physical compute element to the second heterogeneous physical compute element in response to an attempt by the workload to perform at least one of an unsupported instruction and an unsupported architectural feature on the first heterogeneous physical compute element.

Abstract translation: 一方面的处理器包括具有第一组支持的指令和架构特征的第一异构物理计算元件，以及具有第二组支持的指令和架构特征的第二异构物理计算元件。 第二组支持的指令和架构特征与第一组支持的指令和架构特征不同。 处理器还包括与第一和第二异构物理计算元件耦合的工作负载和架构状态迁移模块。 工作负载和状态迁移模块可操作以响应于工作负载尝试执行不支持的指令和不支持的指令中的至少一个而将工作负载和相关联的架构状态从第一异构物理计算元件迁移到第二异构物理计算元件 第一个异构物理计算元素的架构特征。