公开(公告)号：US20170185403A1

公开(公告)日：2017-06-29

申请号：US14757776

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Michael J. Anderson ,  Sheng R. Li ,  Jong Soo Park ,  Md Mostofa Ali Patwary ,  Nadathur Rajagopalan Satish ,  Mikhail Smelyanskiy ,  Narayanan Sundaram

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/3005 ,  G06F9/3877 ,  G06F12/0875 ,  G06F16/9014 ,  G06F17/10 ,  G06F2212/452

Abstract: A processor includes a front end to receive an instruction, a decoder to decode the instruction, a set operations logic unit (SOLU) to execute the instruction, and a retirement unit to retire the instruction. The SOLU includes logic to store a first set of key-value pairs in a content-associative data structure, to receive a second set of key-value pairs, and to identify key-value pairs in the two sets with matching keys. The SOLU includes logic to add the second set of key-value pairs to the first set to produce an output set, and to apply an operation to the values of key-value pairs with matching keys, generating a single value for the matching key. The SOLU includes logic to produce an output set that includes key-value pairs from the first set with matching keys, and to discard key-value pairs from the first set with unique keys.