公开(公告)号：US20240063274A1

公开(公告)日：2024-02-22

申请号：US17889986

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Patrick WALLACE ,  Robert EHLERT ,  Subrina RAFIQUE ,  Peter WELLS ,  Anand S. MURTHY ,  Shishir PANDYA ,  Xiaochen REN ,  Yulia TOLSTOVA

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/24

Abstract: In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires laterally spaced apart from a second vertical stack of horizontal nanowires. An epitaxial source or drain structure is between the first and second vertical stacks of horizontal nanowires. The epitaxial source or drain structure includes a nucleation layer having a first portion in contact with the first vertical stack of horizontal nanowires and a second portion in contact with the second vertical stack of horizontal nanowires. The nucleation layer includes silicon with arsenic dopants. The epitaxial source or drain structure also includes an epitaxial fill layer laterally between the first and second portions of the nucleation layer. The epitaxial fill layer includes silicon with phosphorous dopants. The epitaxial fill layer has a total atomic concentration of arsenic less than half of a total atomic concentration of arsenic of the nucleation layer.