公开(公告)号：US20240170484A1

公开(公告)日：2024-05-23

申请号：US18425944

申请日：2024-01-29

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Nicholas MINUTILLO ,  Anand MURTHY ,  Aaron BUDREVICH ,  Peter WELLS

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/00 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

公开(公告)号：US20240063274A1

公开(公告)日：2024-02-22

申请号：US17889986

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Patrick WALLACE ,  Robert EHLERT ,  Subrina RAFIQUE ,  Peter WELLS ,  Anand S. MURTHY ,  Shishir PANDYA ,  Xiaochen REN ,  Yulia TOLSTOVA

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/24

Abstract: In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires laterally spaced apart from a second vertical stack of horizontal nanowires. An epitaxial source or drain structure is between the first and second vertical stacks of horizontal nanowires. The epitaxial source or drain structure includes a nucleation layer having a first portion in contact with the first vertical stack of horizontal nanowires and a second portion in contact with the second vertical stack of horizontal nanowires. The nucleation layer includes silicon with arsenic dopants. The epitaxial source or drain structure also includes an epitaxial fill layer laterally between the first and second portions of the nucleation layer. The epitaxial fill layer includes silicon with phosphorous dopants. The epitaxial fill layer has a total atomic concentration of arsenic less than half of a total atomic concentration of arsenic of the nucleation layer.

公开(公告)号：US20200312842A1

公开(公告)日：2020-10-01

申请号：US16368077

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Nicholas MINUTILLO ,  Anand MURTHY ,  Aaron BUDREVICH ,  Peter WELLS

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L23/00

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.