公开(公告)号：US20240014268A1

公开(公告)日：2024-01-11

申请号：US18370586

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66439

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20210408246A1

公开(公告)日：2021-12-30

申请号：US16911771

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US20240347610A1

公开(公告)日：2024-10-17

申请号：US18757013

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Koustav GANGULY ,  Ryan KEECH ,  Subrina RAFIQUE ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Ehren MANNEBACH ,  Mauro KOBRINSKY ,  Gilbert DEWEY

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28556 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41766 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

公开(公告)号：US20240258427A1

公开(公告)日：2024-08-01

申请号：US18605406

申请日：2024-03-14

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20200313001A1

公开(公告)日：2020-10-01

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20240063274A1

公开(公告)日：2024-02-22

申请号：US17889986

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Patrick WALLACE ,  Robert EHLERT ,  Subrina RAFIQUE ,  Peter WELLS ,  Anand S. MURTHY ,  Shishir PANDYA ,  Xiaochen REN ,  Yulia TOLSTOVA

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/24

Abstract: In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires laterally spaced apart from a second vertical stack of horizontal nanowires. An epitaxial source or drain structure is between the first and second vertical stacks of horizontal nanowires. The epitaxial source or drain structure includes a nucleation layer having a first portion in contact with the first vertical stack of horizontal nanowires and a second portion in contact with the second vertical stack of horizontal nanowires. The nucleation layer includes silicon with arsenic dopants. The epitaxial source or drain structure also includes an epitaxial fill layer laterally between the first and second portions of the nucleation layer. The epitaxial fill layer includes silicon with phosphorous dopants. The epitaxial fill layer has a total atomic concentration of arsenic less than half of a total atomic concentration of arsenic of the nucleation layer.

公开(公告)号：US20230317789A1

公开(公告)日：2023-10-05

申请号：US17710841

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Anand S. MURTHY ,  Cory BOMBERGER ,  Subrina RAFIQUE ,  Chi-Hing CHOI ,  Mohammad HASAN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/41783

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with selective silicide contacts thereon are described. In an example, an integrated circuit structure includes a plurality of stacks of nanowires. A plurality of epitaxial source or drain structures is around ends of corresponding ones of the stacks of nanowires. A silicide layer is on an entirety of a top surface of the plurality of epitaxial source or drain structures. A conductive trench contact is on the silicide layer. A dielectric layer is vertically intervening between a portion of the conductive trench contact and the silicide layer.

公开(公告)号：US20210091181A1

公开(公告)日：2021-03-25

申请号：US16580941

申请日：2019-09-24

Applicant: Intel Corporation

Inventor： Ryan KEECH ,  Anand S. MURTHY ,  Nicholas G. MINUTILLO ,  Suresh VISHWANATH ,  Mohammad HASAN ,  Biswajeet GUHA ,  Subrina RAFIQUE

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.