公开(公告)号：US10268122B2

公开(公告)日：2019-04-23

申请号：US15124810

申请日：2014-07-08

Applicant: INTEL CORPORATION

Inventor： Silvio E. Bou-Ghazale ,  Abhik Ghosh ,  Niti Goel

IPC: G03F7/20 ,  G11C5/02 ,  G11C29/00 ,  G06F17/50 ,  G06F11/20

Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.

公开(公告)号：US10217732B2

公开(公告)日：2019-02-26

申请号：US15124817

申请日：2014-06-25

Applicant: INTEL CORPORATION

Inventor： Rany T. Elsayed ,  Niti Goel ,  Silvio E. Bou-Ghazale ,  Randy J. Aksamit

IPC: H01L21/027 ,  G06F17/50 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118 ,  H03K19/00 ,  H01L21/8234 ,  H01L29/16

Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

公开(公告)号：US10026686B2

公开(公告)日：2018-07-17

申请号：US15125964

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Silvio E. Bou-Ghazale ,  Rany T. Elsayed ,  Niti Goel

IPC: H01L27/07 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02

Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.