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公开(公告)号:US10217732B2
公开(公告)日:2019-02-26
申请号:US15124817
申请日:2014-06-25
Applicant: INTEL CORPORATION
Inventor: Rany T. Elsayed , Niti Goel , Silvio E. Bou-Ghazale , Randy J. Aksamit
IPC: H01L21/027 , G06F17/50 , H01L27/02 , H01L27/11 , H01L27/118 , H03K19/00 , H01L21/8234 , H01L29/16
Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
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公开(公告)号:US09720484B2
公开(公告)日:2017-08-01
申请号:US14666165
申请日:2015-03-23
Applicant: Intel Corporation
Inventor: Ming Zhang , Chris Wilkerson , Greg Taylor , Randy J. Aksamit , James Tschanz
IPC: G06F1/26 , G06F1/32 , G06F12/0802
CPC classification number: G06F1/324 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3293 , G06F12/0802 , G06F2212/1028 , Y02D10/13
Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.
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公开(公告)号:US09015507B2
公开(公告)日:2015-04-21
申请号:US14038639
申请日:2013-09-26
Applicant: Intel Corporation
Inventor: Ming Zhang , Chris Wilkerson , Greg Taylor , Randy J. Aksamit , James Tschanz
CPC classification number: G06F1/324 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3293 , G06F12/0802 , G06F2212/1028 , Y02D10/13
Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.
Abstract translation: 这里公开了减少用于诸如高速缓存的存储器的最小电压供应(Vcc)要求的保护带(余量)的方法。
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