公开(公告)号：US20220102365A1

公开(公告)日：2022-03-31

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan HA ,  Chuan LIN ,  Deepak THIMMEGOWDA ,  Zengtao LIU ,  Binh N. NGO ,  Soo-yong PARK

IPC: H01L27/1158 ,  G11C16/04 ,  H01L29/10

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.