公开(公告)号：US20210074338A1

公开(公告)日：2021-03-11

申请号：US16562745

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Ravi H. MOTWANI ,  Chang Wan HA

IPC: G11C7/12 ,  G11C29/44 ,  G11C16/34 ,  G11C16/14 ,  G06F11/07

Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

公开(公告)号：US20220102365A1

公开(公告)日：2022-03-31

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan HA ,  Chuan LIN ,  Deepak THIMMEGOWDA ,  Zengtao LIU ,  Binh N. NGO ,  Soo-yong PARK

IPC: H01L27/1158 ,  G11C16/04 ,  H01L29/10

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

公开(公告)号：US20210193200A1

公开(公告)日：2021-06-24

申请号：US17195579

申请日：2021-03-08

Applicant: Intel Corporation

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Ravi H. MOTWANI ,  Chang Wan HA

IPC: G11C7/12 ,  G06F11/07 ,  G11C16/14 ,  G11C16/34 ,  G11C29/44

Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines. In some examples, identification of open or shorted bit lines can be used to identify read operations involving those open or shorted bit lines as weak in connection with performing soft bit read correction.

公开(公告)号：US20210096634A1

公开(公告)日：2021-04-01

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard FASTOW ,  Shankar NATARAJAN ,  Chang Wan HA ,  Chee LAW ,  Khaled HASNAT ,  Chuan LIN ,  Shafqat AHMED

IPC: G06F1/3234 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.