公开(公告)号：US20220102365A1

公开(公告)日：2022-03-31

申请号：US17032239

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Chang Wan HA ,  Chuan LIN ,  Deepak THIMMEGOWDA ,  Zengtao LIU ,  Binh N. NGO ,  Soo-yong PARK

IPC: H01L27/1158 ,  G11C16/04 ,  H01L29/10

Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

公开(公告)号：US20200090743A1

公开(公告)日：2020-03-19

申请号：US16593868

申请日：2019-10-04

Applicant: Intel Corporation

Inventor： Aliasgar S. MADRASWALA ,  Bharat M. PATHAK ,  Binh N. NGO ,  Naveen VITTAL PRABHU ,  Karthikeyan RAMAMURTHI ,  Pranav KALAVADE

IPC: G11C11/56 ,  G11C8/08 ,  G11C16/26 ,  G11C16/08

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.