公开(公告)号：US20210390058A1

公开(公告)日：2021-12-16

申请号：US16902909

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Sudarshanram Shetty ,  Ping Hang Cheung ,  Aravindh Anantaraman ,  Travis Schluessler

IPC: G06F12/0893 ,  G06F12/0873 ,  G06F12/0862 ,  G06F9/30 ,  G06F9/50 ,  G06F11/30

Abstract: An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.

公开(公告)号：US20230111571A1

公开(公告)日：2023-04-13

申请号：US17484619

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carlos Nava Rodriguez ,  Benjamin Pletcher ,  Yoav Harel ,  Bret Martin ,  Sudarshanram Shetty

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/04

Abstract: Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.

公开(公告)号：US11386013B2

公开(公告)日：2022-07-12

申请号：US16902909

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Sudarshanram Shetty ,  Ping Hang Cheung ,  Aravindh Anantaraman ,  Travis Schluessler

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0893 ,  G06F9/30 ,  G06F9/50 ,  G06F11/30 ,  G06F12/0862 ,  G06F12/0873

Abstract: An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.