公开(公告)号：US20230297508A1

公开(公告)日：2023-09-21

申请号：US17699067

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： TOBIAS ZIRR ,  CARSTEN BENTHIN

IPC: G06F12/0864 ,  G06F12/0837 ,  G06F12/02

CPC classification number: G06F12/0864 ,  G06F12/0837 ,  G06F12/0215

Abstract: Embodiments of the invention include acceleration hardware for performing texture lookups and for interpolation for textures backed by hashed memory layouts. In particular, on a texel fetch, a special texture addressing mode allows integer texel coordinates to be hashed and combined with dedicated hardware, to arrive at a pseudo-random memory address for each texel within the memory block allocated to back the respective sampled texture.

公开(公告)号：US20230297415A1

公开(公告)日：2023-09-21

申请号：US17699058

申请日：2022-03-18

Applicant: INTEL CORPORATION

Inventor： PAWEL MAJEWSKI ,  PRASOONKUMAR SURTI ,  TOBIAS ZIRR

IPC: G06F9/48 ,  G06T1/20 ,  G06F9/30

CPC classification number: G06F9/4843 ,  G06T1/20 ,  G06F9/30189

Abstract: Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.