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公开(公告)号：US20220058853A1
公开(公告)日：2022-02-24
申请号：US17500631
申请日：2021-10-13
Applicant: Intel Corporation
Inventor： HUGUES LABBE , DARREL PALKE , SHERINE ABDELHAK , JILL BOYCE , VARGHESE GEORGE , SCOTT JANUS , ADAM LAKE , ZHIJUN LEI , ZHENGMIN LI , MIKE MACPHERSON , CARL MARSHALL , SELVAKUMAR PANNEER , PRASOONKUMAR SURTI , KARTHIK VEERAMANI , DEEPAK VEMBAR , VALLABHAJOSYULA SRINIVASA SOMAYAZULU
Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
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公开(公告)号：US20210150770A1
公开(公告)日：2021-05-20
申请号：US17095544
申请日：2020-11-11
Applicant: Intel Corporation
Inventor： ABHISHEK R. APPU , PRASOONKUMAR SURTI , JILL BOYCE , SUBRAMANIAM MAIYURAN , MICHAEL APODACA , ADAM T. LAKE , JAMES HOLLAND , VASANTH RANGANATHAN , ALTUG KOKER , LIDONG XU , NIKOS KABURLASOS
Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.
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公开(公告)号：US20210041934A1
公开(公告)日：2021-02-11
申请号：US17080395
申请日：2020-10-26
Applicant: Intel Corporation
Inventor： KINCHIT DESAI , SANJEEV JAHAGIRDAR , PRASOONKUMAR SURTI , JOYDEEP RAY
IPC: G06F1/3237 , G06N3/04 , G06N3/08 , G06F1/3234 , G06F1/3206
Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.
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公开(公告)号：US20200211231A1
公开(公告)日：2020-07-02
申请号：US16235672
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , CARSTEN BENTHIN , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , PRASOONKUMAR SURTI , THOMAS RAOUX
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US20190318550A1
公开(公告)日：2019-10-17
申请号：US16383849
申请日：2019-04-15
Applicant: Intel Corporation
Inventor： BARATH LAKSHAMANAN , LINDA l. HURD , BEN J. ASHBAUGH , ELMOUSTAPHA OULD-AHMED-VALL , LIWEI MA , JINGYI JIN , JUSTIN E. GOTTSCHLICH , CHANDRASEKARAN SAKTHIVEL , MICHAEL S. STRICKLAND , BRIAN T. LEWIS , LINDSEY KUPER , ALTUG KOKER , ABHISHEK R. APPU , PRASOONKUMAR SURTI , JOYDEEP RAY , BALAJI VEMBU , JAVIER S. TUREK , NAILA FAROOQUI
IPC: G07C5/00 , G06F9/50 , H04W28/08 , B60W30/00 , H04L29/08 , G01C21/34 , G05D1/00 , G08G1/01 , G06N20/00
Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.
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Patent Agency Ranking
公开(公告)号：US20200210246A1
公开(公告)日：2020-07-02
申请号：US16696848
申请日：2019-11-26
Applicant: Intel Corporation
Inventor： PRASOONKUMAR SURTI , DAVID COWPERTHWAITE , ABHISHEK R. APPU , JOYDEEP RAY , VASANTH RANGANATHAN , ALTUG KOKER , BALAJI VEMBU
IPC: G06F9/50
Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.
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7.发明申请公开(公告)号：US20200045285A1
公开(公告)日：2020-02-06
申请号：US16050322
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： MAYURESH VARERKAR , STANLEY BARAN , MICHAEL APODACA , PRASOONKUMAR SURTI , ATSUO KUWAHARA , NARAYAN BISWAL , JILL BOYCE , YI-JEN CHIU , GOKCEN CILINGIR , BARNAN DAS , ATUL DIVEKAR , SRIKANTH POTLURI , NILESH SHAH , ARCHIE SHARMA
IPC: H04N13/111 , H04N19/597 , G06F3/01 , G06F9/38 , G06F15/18
Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
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公开(公告)号：US20230359496A1
公开(公告)日：2023-11-09
申请号：US17589689
申请日：2022-01-31
Applicant: Intel Corporation
Inventor： PAWEL MAJEWSKI , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , JOSHUA BARCZAK , VASANTH RANGANATHAN , VIKRANTH VEMULAPALLI
CPC classification number: G06F9/5027 , G06F9/4881 , G06F9/54
Abstract: Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.
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公开(公告)号：US20200211261A1
公开(公告)日：2020-07-02
申请号：US16235744
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： SCOTT JANUS , PRASOONKUMAR SURTI , KARTHIK VAIDYANATHAN , GABOR LIKTOR , CARSTEN BENTHIN , PHILIP LAWS
Abstract: Apparatus and method for general ray tracing queries. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes associated with a graphics scene; traversal/intersection hardware logic to traverse one or more rays through the acceleration data structure to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; shape processing hardware logic to specify three dimensional (3D) shape data indicating one or more 3D shapes to be used to perform queries with respect to the hierarchical acceleration data structure; query processing hardware logic to execute queries comprising comparisons between nodes of the hierarchical acceleration data structure and the 3D shape data to generate a result indicating overlap between the 3D shapes and the nodes.
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10.发明申请公开(公告)号：US20200005516A1
公开(公告)日：2020-01-02
申请号：US16024821
申请日：2018-06-30
Applicant: Intel Corporation
Inventor： MICHAEL APODACA , ANKUR SHAH , BEN ASHBAUGH , BRANDON FLIFLET , HEMA NALLURI , PATTABHIRAMAN K , PETER DOYLE , JOSEPH KOSTON , JAMES VALERIO , MURALI RAMADOSS , ALTUG KOKER , ADITYA NAVALE , PRASOONKUMAR SURTI , BALAJI VEMBU
IPC: G06T15/00
Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
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