公开(公告)号：US20160011872A1

公开(公告)日：2016-01-14

申请号：US14327375

申请日：2014-07-09

Applicant: Intel Corporation

Inventor： TOBY OPFERMAN ,  JAMES B. CROSSLAND ,  JASON W. BRANDT ,  BEEMAN C. STRONG

IPC: G06F9/30

CPC classification number: G06F9/30123 ,  G06F9/30145 ,  G06F9/3877 ,  G06F11/3024 ,  G06F11/3079 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/36 ,  G06F11/3636 ,  G06F11/3656

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

Abstract translation: 描述用于产生抑制地址迹线的方法和装置。 在一些实施例中，处理器包括具有跟踪抑制器的跟踪发生器，该跟踪抑制器输出用于由处理器执行的指令的抑制地址跟踪。 在一些实施例中，用于为处理器生成抑制地址轨迹的方法包括从处理器的跟踪发生器的跟踪抑制器产生已执行指令的抑制地址轨迹。

公开(公告)号：US20210245046A1

公开(公告)日：2021-08-12

申请号：US17168299

申请日：2021-02-05

Applicant: Intel Corporation

Inventor： MAKARAND DHARMAPURIKAR ,  RAJABALI KODURI ,  VIJAY BAHIRJI ,  TOBY OPFERMAN ,  SCOTT G. CHRISTIAN ,  RAJEEV PENMATSA ,  SELVAKUMAR PANNEER

IPC: A63F13/355

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

公开(公告)号：US20210406019A1

公开(公告)日：2021-12-30

申请号：US16914343

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： TOBY OPFERMAN ,  PRASHANT SETHI ,  ABHIMANYU K. VARDE ,  BARRY E. HUNTLEY ,  MICHAEL W. Chynoweth ,  JASON W. BRANDT

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.

公开(公告)号：US20170102947A1

公开(公告)日：2017-04-13

申请号：US15384300

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： TOBY OPFERMAN ,  JAMES B. CROSSLAND ,  JASON W. BRANDT ,  BEEMAN C. STRONG

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30123 ,  G06F9/30145 ,  G06F9/3877 ,  G06F11/3024 ,  G06F11/3079 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/36 ,  G06F11/3636 ,  G06F11/3656

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.